• Corpus ID: 212568553

Leakage current reduction in CMOS circuits using stacking effect

  title={Leakage current reduction in CMOS circuits using stacking effect},
  author={Nikhil Saxena and Sonal Soni},
Volume 2, Issue 11, November 2013 Page 213 Abstract Due to the growing impact of subthreshold and gate leakage, static leakage is contributing more and more towards the power dissipation in deep submicron Nano CMOS technology. There have been many works on subthreshold leakage and techniques to reduce it, such as controlling the input vector to the circuit in standby mode, forcing stack and body bias control. In this tutorial paper we have reviewed the leakage current with change in drain… 

Tables from this paper

Estimation of Power and Delay in CMOS Circuits using Leakage Control Transistor
Abstract With a rapid growth in semiconductor Industry, complex applications are being implemented using small size chips, with the use of Complementary Metal Oxide Semi-Conductors (CMOS). With the
Stack Contention-alleviated Precharge Keeper for Pseudo Domino Logic
Different design topologies on the domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation and delay are provided.
Low-power stack pseudo domino logic using contention-alleviated precharge keeper
  • Deepika Bansal, B. Singh, Ajay Kumar
  • Engineering
    2016 International Conference on Information Technology (InCITe) - The Next Generation IT Summit on the Theme - Internet of Things: Connect your Worlds
  • 2016
Different design topologies on the pseudo domino circuits to overcome the charge sharing and charge leakage with reference to the power dissipation are provided.
Multi-Threshold CMOS Devices: A Comparative Analysis of Leakage Power and Delay in Digital Circuits for Nano-Scale Technology
Four widely used D flip flop integrated circuits are taken as examples and analyzed with MTCMOS - LVT & HVT separately and various performance parameters such as total power, leakage power, propagation delay & leakage power and delay product (PDP) are analyzed.
Static power characteristics of selective buried oxide CMOS devices
Selective buried oxide (SELBOX) Metal‐Oxide‐Semiconductor Field‐Effect Transistor (MOSFET) structure can be used to reduce the kink effect and self‐heating problems associated with the silicon on
Low power high speed D flip flop design using improved SVL technique
  • G. Sushma, V. Ramesh
  • Engineering
    2016 International Conference on Recent Trends in Information Technology (ICRTIT)
  • 2016
A new D flip flop design is proposed which employs improved SVL technique in order to reduce power consumption due to leakage currents in standby mode and uses less number of clocked transistors, thus reduces the dynamic power consumption as well as delay compared to existing design.
Analysis of the implications of stacked devices in nano-scale technologies for analog applications
A methodology to assess the implications on the performance of analog circuits due to the use of stacked devices in current nano-scale technologies is presented and helps designers to develop a good understanding of the characteristics and limitations of a particular physical design before silicon is back for laboratory testing.
Temperature Aware Design for High Performance Processors
Results shows that, the appropriate thermal management system can be designed for a much lower maximum power rating with minimal performance impact for typical applications, considerable amount of power consumption reduction as well as thermal aware challenges have been obtained.
Power Characteristics of Selective Buried Oxide MOSFET
A Master of Science thesis in Electrical Engineering by Dana Tariq Younis entitled, "Power Characteristics of Selective Buried Oxide MOSFET," submitted in January 2016. Thesis advisor is Dr. Hasan
Stacked-FET based GaAs monolithic microwave high-power amplifiers for active electronically scanned array radar front-ends
The reported results demonstrate that GaAs Stacked-FET power amplifiers, designed according to the strategy defined in this thesis, can deliver an output power in excess of 25 W with a PAE higher than 40 % over a bandwidth of 30 % at S-band frequencies.


Scaling of stack effect and its application for leakage reduction
A model that predicts the scaling nature of this leakage reduction effect is presented and use of stack effect for leakage reduction and other implications of this effect are discussed.
Analysis and minimization techniques for total leakage considering gate oxide leakage
A fast approach to analyze the total leakage power of a large circuit block, considering both I/sub gate/ and subthreshold leakage (I/sub sub/), and proposes the use of pin recording as a means to reduce I/ sub gate/ due to the dependencies of gate leakage on stack node voltages.
A model for leakage control by MOS transistlor stacking
Prevailing CMOS design practice has been very conservative with regard t o choice of transistor threshold voltage, so as t o avoid the difficult problems of threshold variations and high leakage
Leakage current reduction in CMOS VLSI circuits by input vector control
Two runtime mechanisms for reducing the leakage current of a CMOS circuit are described and a design technique for applying the minimum leakage input to a sequential circuit is presented, which shows that it is possible to reduce the leakage by an average of 25% with practically no delay penalty.
A combined gate replacement and input vector control approach for leakage current reduction
  • Lin Yuan, G. Qu
  • Engineering, Computer Science
    IEEE Trans. Very Large Scale Integr. Syst.
  • 2006
A divide-and-conquer approach is presented that integrates gate replacement, an optimal MLV searching algorithm for tree circuits, and a genetic algorithm to connect the tree circuits to overcome the limitation of internal gates at high logic levels.
Leakage in Nanoscale CMOS Technologies
  • 2005
Accurate Macro-modeling for Leakage Current for IDDQ Test.
  • Instrumentation and Measurement Technology Conference Proceedings,
  • 2007