Leakage Power Reduction in CMOS VLSI Circuits

@article{Saini2012LeakagePR,
  title={Leakage Power Reduction in CMOS VLSI Circuits},
  author={Pushpa Saini and Rajesh Mehra},
  journal={International Journal of Computer Applications},
  year={2012},
  volume={55},
  pages={42-48}
}
  • Pushpa Saini, R. Mehra
  • Published 20 October 2012
  • Engineering
  • International Journal of Computer Applications
Leakage power has become a serious concern in nanometer CMOS technologies. In the past, the dynamic power has dominated the total power dissipation of CMOS devices. However, with the continuous trend of technology scaling, leakage power is becoming a main contributor to power consumption. In the past many methods had been proposed for leakage power reduction like forced stack, sleepy stack, sleepy keeper, dual sleep approach etc. using techniques like transistor sizing, multi-Vth, dual-Vth… 
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