Leakage Power Reduction in CMOS VLSI Circuits

@article{Saini2012LeakagePR,
  title={Leakage Power Reduction in CMOS VLSI Circuits},
  author={Pushpa Saini and Rajesh Mehra},
  journal={International Journal of Computer Applications},
  year={2012},
  volume={55},
  pages={42-48}
}
  • Pushpa Saini, R. Mehra
  • Published 20 October 2012
  • Engineering
  • International Journal of Computer Applications
Leakage power has become a serious concern in nanometer CMOS technologies. In the past, the dynamic power has dominated the total power dissipation of CMOS devices. However, with the continuous trend of technology scaling, leakage power is becoming a main contributor to power consumption. In the past many methods had been proposed for leakage power reduction like forced stack, sleepy stack, sleepy keeper, dual sleep approach etc. using techniques like transistor sizing, multi-Vth, dual-Vth… 

Figures and Tables from this paper

A NOVEL APPROACH FOR LEAKAGE POWER REDUCTION TECHNIQUES IN CMOS VLSI CIRCUITS
TLDR
New methods have been proposed for leakage power reduction in 45 nm technology and the performance parameters of proposed methods are compared with the previous standard leakage reduction techniques using microwind software.
Reduction of leakage power in CMOS circuits using efficient variable body biasing with bypass technique
  • Engineering, Computer Science
  • 2020
TLDR
The proposed efficient variable body biasing with bypass (EVBB) technique gives better significant result than the previous existing leakage reduction techniques by reducing the time delay and area of the CMOS circuits.
Leakage Power Reduction Techniques for Nanoscale CMOS VLSI Systems and Effect of Technology Scaling on Leakage Power
TLDR
A comprehensive study and analysis of various leakage power reduction techniques have been presented and the effect of technology scaling on the leakage power is analysed.
MULTITHRESHOLD CMOS SLEEP STACK AND LOGIC STACK TECHNIQUE FOR DIGITAL CIRCUIT DESIGN
Power optimization is the major problem in digital circuit design. In this paper using MTCMOS and stack techniques are proposed. Multi threshold CMOS sleep stack and logic stack, super cutoff sleep
Various Low Power Approaches in CMOS Vlsi Circuits
TLDR
Some techniques have been introduced which are helpful in leakage power reduction and will be compared with past techniques and the result have been simulated using tanner EDA 15.11 tool in 0.5micron CMOS technology.
Novel Low Leakage Power Technique of LSP in 32 nm VLSI Circuits
TLDR
A novel approach at circuit level named LSP is proposed by combination of LECTOR, Stack and Pass transistors techniques to decrease leakage power dissipation during active and standby mode to maintain logic state of network in the standby mode.
Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)
Currently, energy consumption in the digital circuit is a key design parameter for emerging mobile products. The principal cause of the power dissipation during idle mode is leakage currents, which
Power Optimization Techniques at Circuit and Device Level in Digital CMOS VLSI – A Review
  • A. Babu
  • Computer Science, Engineering
  • 2014
TLDR
Insight is put into the various sources of power dissipation in digital CMOS and the power optimization techniques at circuit and device level and the various methods to speed up digital circuits and to reduce the area of their design.
Design and analysis of low run-time leakage in a 10 Transistors full adder in 45nm technology
In this paper the different topologies of one bit full adders including the most interesting of one proposed is analysed and compared for peak leakage,average leakage, peak power and average power.
Analysis of Power Efficient 6-T SRAM Cell with Performance Measurements
  • Neha Raghav, Malti Bansal
  • Engineering
    2017 International Conference on Innovations in Control, Communication and Information Systems (ICICCI)
  • 2017
TLDR
A comparative study of various leakage power reduction techniques like Schmitt trigger, forced stack technique and LECTOR technique with SRAM architecture has been done and results show that the SRAM cell usingforced stack technique attains lowest static power dissipation and total power Dissipation along with all the advantages of the existing SRAM Cell.
...
...

References

SHOWING 1-10 OF 18 REFERENCES
A novel leakage power reduction technique for CMOS circuit design
Power consumption is now a major technical problem facing the CMOS circuits in deep submicron process. As process moves to finer technologies, leakage power significantly increases very rapidly due
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits
TLDR
A novel, layout-aware methodology is proposed that facilitates sleep transistor insertion and virtual-ground routing on row-based layouts and introduces a clustering algorithm that is able to handle simultaneously timing and area constraints.
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
TLDR
The proposed approach demonstrates that the optimal body bias reduces a considerable amount of standby leakage power dissipation in nanoscale CMOS integrated circuits.
Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design
  • Se Hun Kim, V. Mooney
  • Computer Science
    2006 IFIP International Conference on Very Large Scale Integration
  • 2006
TLDR
The sleepy keeper approach provides a new weapon in a VLSI designer's arsenal that achieves leakage power reduction equivalent to the sleep and zigzag approaches but with the advantage of maintaining exact logic state when sleep mode is entered.
Dual stack method: A novel approach to low leakage and speed power product VLSI design
TLDR
A new dual stack approach for reducing both leakage and dynamic powers is proposed and shows the least speed power product when compared to the existing methods.
Sleepy Stack Reduction of Leakage Power
TLDR
This work proposes a novel leakage reduction technique, named “sleepy stack,” which can be applied to general logic design and retains exact logic state, making it better than traditional sleep and zigzag techniques while saving leakage power consumption.
Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits
TLDR
Circuit optimization and design automation techniques are introduced to bring leakage under control in CMOS circuits and present techniques for active leakage control.
Low Power , Reduced Dynamic Voltage Swing Domino Logic Circuits
TLDR
New reduced – swing domino logic techniques which provide significant low power dissipation as compared to traditional domino circuit structures are proposed.
CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff
A mixed integer linear programming (MILP) technique simultaneously minimizes the leakage and glitch power consumption of a static CMOS circuit for any specified input to output delay. Using
Leakage in Nanometer CMOS Technologies
Covers in detail promising solutions at the device, circuit, and architecture levels of abstraction after first explaining the sensitivity of the various MOS leakage sources to these conditions from
...
...