Leakage Power Reduction in CMOS VLSI Circuits
@article{Saini2012LeakagePR, title={Leakage Power Reduction in CMOS VLSI Circuits}, author={Pushpa Saini and Rajesh Mehra}, journal={International Journal of Computer Applications}, year={2012}, volume={55}, pages={42-48} }
Leakage power has become a serious concern in nanometer CMOS technologies. In the past, the dynamic power has dominated the total power dissipation of CMOS devices. However, with the continuous trend of technology scaling, leakage power is becoming a main contributor to power consumption. In the past many methods had been proposed for leakage power reduction like forced stack, sleepy stack, sleepy keeper, dual sleep approach etc. using techniques like transistor sizing, multi-Vth, dual-Vth…
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References
SHOWING 1-10 OF 18 REFERENCES
A novel leakage power reduction technique for CMOS circuit design
- Engineering2010 International SoC Design Conference
- 2010
Power consumption is now a major technical problem facing the CMOS circuits in deep submicron process. As process moves to finer technologies, leakage power significantly increases very rapidly due…
Row-Based Power-Gating: A Novel Sleep Transistor Insertion Methodology for Leakage Power Optimization in Nanometer CMOS Circuits
- Computer ScienceIEEE Transactions on Very Large Scale Integration (VLSI) Systems
- 2011
A novel, layout-aware methodology is proposed that facilitates sleep transistor insertion and virtual-ground routing on row-based layouts and introduces a clustering algorithm that is able to handle simultaneously timing and area constraints.
Standby Leakage Power Reduction Technique for Nanoscale CMOS VLSI Systems
- EngineeringIEEE Transactions on Instrumentation and Measurement
- 2010
The proposed approach demonstrates that the optimal body bias reduces a considerable amount of standby leakage power dissipation in nanoscale CMOS integrated circuits.
Sleepy Keeper: a New Approach to Low-leakage Power VLSI Design
- Computer Science2006 IFIP International Conference on Very Large Scale Integration
- 2006
The sleepy keeper approach provides a new weapon in a VLSI designer's arsenal that achieves leakage power reduction equivalent to the sleep and zigzag approaches but with the advantage of maintaining exact logic state when sleep mode is entered.
Dual stack method: A novel approach to low leakage and speed power product VLSI design
- Computer ScienceInternational Conference on Electrical & Computer Engineering (ICECE 2010)
- 2010
A new dual stack approach for reducing both leakage and dynamic powers is proposed and shows the least speed power product when compared to the existing methods.
Sleepy Stack Reduction of Leakage Power
- Computer SciencePATMOS
- 2004
This work proposes a novel leakage reduction technique, named “sleepy stack,” which can be applied to general logic design and retains exact logic state, making it better than traditional sleep and zigzag techniques while saving leakage power consumption.
Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits
- EngineeringIEICE Trans. Electron.
- 2005
Circuit optimization and design automation techniques are introduced to bring leakage under control in CMOS circuits and present techniques for active leakage control.
Low Power , Reduced Dynamic Voltage Swing Domino Logic Circuits
- Computer Science
- 2010
New reduced – swing domino logic techniques which provide significant low power dissipation as compared to traditional domino circuit structures are proposed.
CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff
- EngineeringJ. Low Power Electron.
- 2006
A mixed integer linear programming (MILP) technique simultaneously minimizes the leakage and glitch power consumption of a static CMOS circuit for any specified input to output delay. Using…
Leakage in Nanometer CMOS Technologies
- Engineering
- 2010
Covers in detail promising solutions at the device, circuit, and architecture levels of abstraction after first explaining the sensitivity of the various MOS leakage sources to these conditions from…