Leakage Power Reduction for CMOS Combinational Circuits


In this paper, the problem of leakage power reduction by means of input vector control was studied, and a platform for CMOS combinational circuit leakage power reduction was developed. Genetic algorithm is used for searching minimum leakage vector with circuit status difference as fitness function. Experimental results indicate that the method can achieve satisfied leakage power reduction, and the run time is reasonable. This method has no requirement for Spice simulation and independent from target technology

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@article{Zhao2006LeakagePR, title={Leakage Power Reduction for CMOS Combinational Circuits}, author={Xiaoying Zhao and Jiangfang Yi and Dong Tong and Xu Cheng}, journal={2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings}, year={2006}, pages={1621-1623} }