Leakage Characterization of Top Select Transistor for Program Disturbance Optimization in 3D NAND Flash

@inproceedings{Zhang2017LeakageCO,
  title={Leakage Characterization of Top Select Transistor for Program Disturbance Optimization in 3D NAND Flash},
  author={Yu Zhang and Lei Jin and Dandan Jiang and Xingqi Zou and Zhiguo Zhao and Jing Gao and Ming Zeng and Wenbin Zhou and Zhaoyun Tang and Zongliang Huo},
  year={2017}
}
• A characterization approach that measures top select transistor (TSG) leakage from bit-line is proposed to quantify TSG leakage under program inhibit condition in 3D NAND flash memory. 

Citations

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Cycling Induced Trap Generation and Recovery Near the Top Select Gate Transistor in 3D NAND

  • 2019 IEEE International Reliability Physics Symposium (IRPS)
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Investigation of Erase Cycling Induced TSG Vt Shift in 3D NAND Flash Memory

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A Novel Program Scheme for Program Disturbance Optimization in 3-D NAND Flash Memory

Yu Zhang, Lei Jin, +3 authors Zongliang Huo
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