Leading-Zero Anticipatory Logic for High-Speed Floating Point Addition - Solid-State Circuits, IEEE Journal of


This paper describes a new leading-zero anticipatory (LZA) logic for high-speed floating-point addition (FADD). This logic carries out the pre-decoding for normalization concurrently with addition for the significand. It also performs the shift operation of normalization in parallel with the rounding operation. The use of simple Boolean algebra allows the… (More)


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