LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels

@article{Stecklina1970LazyFPLF,
  title={LazyFP: Leaking FPU Register State using Microarchitectural Side-Channels},
  author={Julian Stecklina and Thomas Prescher},
  journal={CoRR},
  year={1970},
  volume={abs/1806.07480}
}
Modern processors utilize an increasingly large register set to facilitate efficient floating point and SIMD computation. This large register set is a burden for operating systems, as its content needs to be saved and restored when the operating system context switches between tasks. As an optimization, the operating system can defer the context switch of the FPU and SIMD register set until the first instruction is executed that needs access to these registers. Meanwhile, the old content is… CONTINUE READING