Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks

Abstract

In this paper, the major methodologies proposed in the last years to speed-up the synthesis of radio-frequency integrated circuits blocks are overviewed. The challenges to automate this task are discussed, and, to avoid non-systematic iterations between circuit and layout design steps, the architecture of an innovative solution is proposed. The proposed… (More)

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Cite this paper

@article{Martins2017LayoutawareCA, title={Layout-aware challenges and a solution for the automatic synthesis of radio-frequency IC blocks}, author={R. Martins and N. Lourenx00E7o and R. Px00F3voa and Amparo Calleja Canelas and Nuno Horta and F{\'a}bio Passos and R. Castro-Lx00F3pez and E. Roca and F. O. Fernx00E1ndez}, journal={2017 14th International Conference on Synthesis, Modeling, Analysis and Simulation Methods and Applications to Circuit Design (SMACD)}, year={2017}, pages={1-4} }