Layout Technique for Single-Event Transient Mitigation via Pulse Quenching

  title={Layout Technique for Single-Event Transient Mitigation via Pulse Quenching},
  author={Nicholas M. Atkinson and A. F. Witulski and W. Timothy Holman and J. R. Ahlbin and B. L. Bhuva and L. W. Massengill},
  journal={IEEE Transactions on Nuclear Science},
A layout technique that exploits single-event transient pulse quenching to mitigate transients in combinational logic is presented. TCAD simulations show as much as 60% reduction in sensitive area and 70% reduction in pulse width for some logic cells. 
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The effect of layout topology on single-event transient pulse quenching in a 65 nm bulk CMOS process

  • J. R. Ahlbin, M. J. Gadlage, B. L. Bhuva, R. A. Reed, G. Vizkelethy, L. W. Massengill
  • IEEE Trans. Nucl. Sci., vol. 57, no. 6, pp. 3380…
  • 2010
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