Layout Technique for Single-Event Transient Mitigation via Pulse Quenching

@article{Atkinson2011LayoutTF,
  title={Layout Technique for Single-Event Transient Mitigation via Pulse Quenching},
  author={Nicholas M. Atkinson and A. F. Witulski and W. Timothy Holman and J. R. Ahlbin and B. L. Bhuva and L. W. Massengill},
  journal={IEEE Transactions on Nuclear Science},
  year={2011},
  volume={58},
  pages={885-890}
}
A layout technique that exploits single-event transient pulse quenching to mitigate transients in combinational logic is presented. TCAD simulations show as much as 60% reduction in sensitive area and 70% reduction in pulse width for some logic cells. 
Highly Cited
This paper has 107 citations. REVIEW CITATIONS

Citations

Publications citing this paper.
Showing 1-10 of 34 extracted citations

108 Citations

02040'12'14'16'18
Citations per Year
Semantic Scholar estimates that this publication has 108 citations based on the available data.

See our FAQ for additional information.

References

Publications referenced by this paper.
Showing 1-10 of 12 references

The effect of layout topology on single-event transient pulse quenching in a 65 nm bulk CMOS process

  • J. R. Ahlbin, M. J. Gadlage, B. L. Bhuva, R. A. Reed, G. Vizkelethy, L. W. Massengill
  • IEEE Trans. Nucl. Sci., vol. 57, no. 6, pp. 3380…
  • 2010
2 Excerpts

Similar Papers

Loading similar papers…