Layout-Aware Selection of Trace Signals for Post-Silicon Debug


Post-silicon debug is widely acknowledged as a bottleneck in SoC design methodology. A major challenge during post-silicon debug is the limited observability of internal signals. Existing approaches try to select a small set of beneficial trace signals that can maximize observability. Unfortunately, these techniques do not consider design constraints such… (More)
DOI: 10.1109/ISVLSI.2014.19


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