Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs

  title={Layout Aware Optimization of High Speed Fixed Coefficient FIR Filters for FPGAs},
  author={Shahnam Mirzaei and Ryan Kastner and Anup Hosangadi},
  journal={Int. J. Reconfig. Comp.},
We present a method for implementing high speed finite impulse response (FIR) filters on field programmable gate arrays (FPGAs). Our algorithm is a multiplierless technique where fixed coefficient multipliers are replaced with a series of add and shift operations. The first phase of our algorithm uses registered adders and hardwired shifts. Here, a modified common subexpression elimination (CSE) algorithm reduces the number of adders while maintaining performance. The second phase optimizes… CONTINUE READING

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Key Quantitative Results

  • We observed up to 50% reduction in the number of slices and up to 75% reduction in the number of look up tables (LUTs) for fully parallel implementations compared to DA method. Also, there is 50% reduction in the total dynamic power consumption of the filters. Our designs perform up to 27% faster than the multiply accumulate (MAC) filters implemented by Xilinx Coregen tool using DSP blocks.


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