Large-scale circuit placement

@article{Cong2005LargescaleCP,
  title={Large-scale circuit placement},
  author={Jason Cong and Joseph R. Shinnerl and Min Xie and Tim Kong and Xin Yuan},
  journal={ACM Trans. Design Autom. Electr. Syst.},
  year={2005},
  volume={10},
  pages={389-430}
}
Placement is one of the most important steps in the RTL-to-GDSII synthesis process, as it directly defines the interconnects, which have become the bottleneck in circuit and system performance in deep submicron technologies. The placement problem has been studied extensively in the past 30 years. However, recent studies show that existing placement solutions are surprisingly far from optimal. The first part of this tutorial summarizes results from recent optimality and scalability studies of… Expand
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References

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TLDR
This study reveals the gap between the results produced by these tools versus true optimal solutions and finds that the effectiveness of the algorithms varies for circuits with different characteristics, indicating significant room for improvement in existing placement algorithms. Expand
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TLDR
It is argued that net-cut minimization is a good and important shortcut to solve the large scale placement problem and is shown to be more important than greedily obtain a wirelength optimal placement at intermediate hierarchical levels. Expand
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TLDR
A novel approach to performance-driven placement is presented, combining timing analysis and physical design to dynamically optimize the performance of the chip during placement. Expand
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TLDR
An accurate and efficient placement routability modeling technique is proposed and incorporated into the prevailing simulated annealing approach based on the supply versus demand analysis of routing resource over an array of regions on a chip. Expand
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The prevalence of net list synthesis tools raises great concern on routability of cell placement created with state-of-the-art placement techniques. In this paper, an accurate and efficient placementExpand
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Regular structures are present in many types of circuits. If this structure can be identified and utilized, performance can be improved dramatically. In this paper, we present a novel placementExpand
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TLDR
A new class of fast and highly scalable placement algorithms that directly handle complex constraints and achieve total wirelengths comparable to the state of the art are designed and implemented. Expand
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TLDR
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