LRU-WSR: integration of LRU and writes sequence reordering for flash memory


Most mobile devices are equipped with a NAND flash memory even if it has characteristics of not-in-place update and asymmetric I/O latencies among read, write, and erase operations: write/erase operations are much slower than a read operation in a flash memory. For the overall performance of a flash memory system, the buffer replacement policy should consider the above severely asymmetric I/O latencies. However, existing LRU buffer replacement algorithm cannot deal with the above problem. This paper proposes the LRU-WSR buffer replacement algorithm that enhances LRU by reordering writes of not-cold dirty pages from the buffer cache to flash storage. The enhanced LRUWSR algorithm focuses on reducing the number of write/erase operations as well as preventing serious degradation of buffer hit ratio. The experimental results show that the LRU-WSR outperforms other algorithms including LRU, CF-LRU, and FAB. Index Terms — flash memory, buffer replacement, storage system

DOI: 10.1109/TCE.2008.4637609

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@article{Jung2008LRUWSRIO, title={LRU-WSR: integration of LRU and writes sequence reordering for flash memory}, author={Hoyoung Jung and Hyoki Shim and Sungmin Park and Sooyong Kang and Jaehyuk Cha}, journal={IEEE Trans. Consumer Electronics}, year={2008}, volume={54}, pages={1215-1223} }