LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches

@article{Cheng2016LAPLA,
  title={LAP: Loop-Block Aware Inclusion Properties for Energy-Efficient Asymmetric Last Level Caches},
  author={Hsiang-Yun Cheng and Jishen Zhao and Jack Sampson and Mary Jane Irwin and Aamer Jaleel and Yu Lu and Yuan Xie},
  journal={2016 ACM/IEEE 43rd Annual International Symposium on Computer Architecture (ISCA)},
  year={2016},
  pages={103-114}
}
Emerging non-volatile memory (NVM) technologies, such as spin-transfer torque RAM (STT-RAM), are attractive options for replacing or augmenting SRAM in implementing last-level caches (LLCs). However, the asymmetric read/write energy and latency associated with NVM introduces new challenges in designing caches where, in contrast to SRAM, dynamic energy from write operations can be responsible for a larger fraction of total cache energy than leakage. These properties lead to the fact that no… CONTINUE READING

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