Corpus ID: 35025241

Kwong Fabrication and Characterization of Poly-Si Vertical Nanowire Thin Film Transistor P

@inproceedings{Shen2013KwongFA,
  title={Kwong Fabrication and Characterization of Poly-Si Vertical Nanowire Thin Film Transistor P},
  author={Nansheng Shen and T. T. Le and H. Y. Yu and Zhi Xian Chen and K. T. Win and N. Singh and G. Q. Lo},
  year={2013}
}
In this paper, we present a vertical nanowire thin film transistor with gate-all-around architecture, fabricated using CMOS compatible processes. A novel method of fabricating polysilicon vertical nanowires of diameter as small as 30 nm using wet-etch is presented. Both n-type and p-type vertical poly-silicon nanowire transistors exhibit superior electrical characteristics as compared to planar devices. On a poly-crystalline nanowire of 30 nm diameter, high Ion/Ioff ratio of 10, low drain… Expand

Figures from this paper

References

SHOWING 1-3 OF 3 REFERENCES
Vertical Silicon-Nanowire Formation and Gate-All-Around MOSFET
This letter presents a vertical gate-all-around silicon nanowire transistor on bulk silicon wafer utilizing fully CMOS compatible technology. High aspect ratio (up to 50: 1) vertical nanowires withExpand
New Three-Dimensional High-Density Stacked-Surrounding Gate Transistor (S-SGT) Flash Memory Architecture Using Self-Aligned Interconnection Fabrication Technology without Photolithography Process for Tera-Bits and Beyond
New three-dimensional Stacked-Surrounding Gate Transistor (S-SGT) flash memory architecture can achieve the cell area of 3.88F2 per bit using the 0.2 µm design rule. The new architecture is realizedExpand
Performance 30-nm Gate-All-Around Poly-Si Nanowire Thin-Film Transistor With NH3
  • IEEE Electron Device Lett., vol. 31,
  • 2010