Corpus ID: 61911142

Keynote Paper Elastic Circuits

  title={Keynote Paper Elastic Circuits},
  author={J. Carmona and J. Cortadella and M. Kishinevsky and A. Taubin},
Elasticity in circuits and systems provides tolerance to variations in computation and communication delays. This paper presents a comprehensive overview of elastic circuits for those designers who are mainly familiar with synchronous de- sign. Elasticity can be implemented both synchronously and asyn- chronously, although it was traditionally more often associated with asynchronous circuits. This paper shows that synchronous and asynchronous elastic circuits can be designed, analyzed, and… Expand


Pipelined Asynchronous Circuits
A design style for implementing communicating sequential processes (CSP) as quasi delay insensitive asynchronous circuits, based on the compilation method of [1], which can easily implement circuits with some slack between inputs and outputs is presented. Expand
Synchronous Elastic Circuits with Early Evaluation and Token Counterflow
A protocol for latency-insensitive design with early evaluation is presented. The protocol is based on a symmetric view of the system in which tokens carrying information move in the forwardExpand
Robust interfaces for mixed-timing systems
  • T. Chelcea, S. Nowick
  • Computer Science
  • IEEE Transactions on Very Large Scale Integration (VLSI) Systems
  • 2004
This paper presents several low-latency mixed-timing FIFO (first-in-first-out) interfaces designs that interface systems on a chip working at different speeds and initial simulations for both latency and throughput are promising. Expand
The limitations to delay-insensitivity in asynchronous circuits
Asynchronous techniques —that is, techniques that do not use clocks to implement sequencing— are currently attracting considerable interest for digital VLSI circuit design, in particular when theExpand
Performance analysis and optimization of asynchronous circuits
This work adapts the theory of generalized timed Petri-nets (GTPN) for analyzing and comparing asynchronous circuits ranging from purely control-oriented circuits to those with data dependent control. Expand
Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications
This paper proves the feasibility and effectiveness of the proposed approach to desynchronization by showing its application to a set of real designs, including a complete implementation of the DLX microprocessor architecture. Expand
Design criteria for autosynchronous circuits
Circuits which are free of transient logical malfunctions, sometimes called "spikes," will be developed and a typical autosynchronous system will be shown. Expand
Slack Elasticity in Concurrent Computing
Conditions under which the authors can modify the slack of a channel in a distributed computation without changing its behavior can be used to modify the degree of pipelining in an asynchronous system. Expand
Synthesis of synchronous elastic architectures
A formal specification of the protocol is defined and an efficient scheme for the implementation of elasticity that involves no datapath overhead is presented, opening up opportunities for microarchitectural design. Expand
Bridging the gap between asynchronous design and designers
The design methodology of control circuits based on specifications with signal transition graphs is presented and the design of complex circuits with different clock domains and desynchronisation of synchronous circuits is dealt with. Expand