Key Technologies for 500 MHz VLSI Test System "ULTIMATE"

@inproceedings{Tamama1988KeyTF,
  title={Key Technologies for 500 MHz VLSI Test System "ULTIMATE"},
  author={Teruo Tamama and Naoaki Narumi and Taiichi Otsuji and Masao Suzuki and Tsuneta Sudo},
  booktitle={ITC},
  year={1988}
}
2. TIMING SUBSYSTEM This paper describes key technologies needed for constructing ULTIMATE, including an 8-ps resolution timing generator, a formatter with a realtime waveform control function, a 2.5-ps resolution standard comparator, and a miniaturized 3-GHz 59-pole channel selector. Almost all the pin-electronics hardware has been integrated on 12 kinds of LSIs, 8 of which are 2.5K-gate and 400-gate ultra-high speed bipolar gate arrays. ULTIMATE realizes 2 5 5 -ps overall timing accuracy by… CONTINUE READING