Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology

@article{Yamamoto2007JunctionPE,
  title={Junction Profile Engineering with a Novel Multiple Laser Spike Annealing Scheme for 45-nm Node High Performance and Low Leakage CMOS Technology},
  author={Takuji Yamamoto and Tomohiro Kubo and T. Sukegawa and Eiichi Takii and Y. Shimamune and Naoyuki Tamura and Tsunehisa Sakoda and Motohiro Nakamura and Hiroshi Ohta and Toshihiko Miyashita and Hajime Kurata and S. Satoh and Masayuki Kase and Toshihiro Sugii},
  journal={2007 IEEE International Electron Devices Meeting},
  year={2007},
  pages={143-146}
}
We developed novel junction profile engineering that uses a newly developed multiple laser spike annealing scheme and applied it to 45-nm node high performance and low leakage CMOS technology. This novel junction profile engineering is effective for the performance improvement of CMOS devices with embedded SiGe in the PMOS regions. Reduction of the source-drain parasitic resistance and the junction leakage current were achieved, thus improving the Ion of 33-nm CMOS devices (8.2% / 12.8% with an… CONTINUE READING

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