Jitter Characteristic in Charge Recovery Resonant Clock Distribution

@article{Mesgarzadeh2007JitterCI,
  title={Jitter Characteristic in Charge Recovery Resonant Clock Distribution},
  author={Behzad Mesgarzadeh and Marcus Hansson and Atila Alvandpour},
  journal={IEEE Journal of Solid-State Circuits},
  year={2007},
  volume={42},
  pages={1618-1625}
}
This paper is focused on analysis and suppression of clock jitter in charge recovery resonant clock distribution networks. In the presented analysis, by considering the data-dependent nature of the generated jitter, the reason for the undesired jitter-peaking phenomenon is investigated. The analysis has been verified by measurements on a test chip fabricated in 0.13-mum standard CMOS process. The chip includes a fully integrated 1.5-GHz LC clock resonator with a passive (bufferless) clock… CONTINUE READING

Figures, Results, and Topics from this paper.

Key Quantitative Results

  • Measurement results show about 50% peak-to-peak clock jitter reduction from 28.4 ps down to 14.5 ps after injection locking.
  • In addition, in order to reduce the large data-dependent clock jitter, we have proposed a jitter-suppression technique based on injection locking, which has reduced the worst-case peak-to-peak jitter by 50%.

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