JIT trace-based verification for high-level synthesis

@article{Yang2015JITTV,
  title={JIT trace-based verification for high-level synthesis},
  author={Liwei Yang and Magzhan Ikram and Swathi T. Gurumani and Suhaib A. Fahmy and Deming Chen and Kyle Rupnow},
  journal={2015 International Conference on Field Programmable Technology (FPT)},
  year={2015},
  pages={228-231}
}
High level synthesis (HLS) tools are increasingly adopted for hardware design as the quality of tools consistently improves. Concerted development effort on HLS tools represents significant software development effort, and debugging and validation represents a significant portion of that effort. However, HLS tools are different from typical large-scale software systems; HLS tool output must be subsequently verified through functional verification of the generated RTL implementation. Debugging… CONTINUE READING

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