Iterative Performance Model Upgradation in Geometric Programming Based Analog Circuit Sizing for Improved Design Accuracy

Abstract

In this paper, we propose a technique to improve the accuracy of the final design predicted by Geometric Programming based CMOS analog circuit sizing methodology. Here we use a multi-level AC performance modeling paradigm to develop the empirical models of circuit performance metrics. Performance models are then upgraded over iterations of design cycle… (More)
DOI: 10.1109/VLSID.2012.100

Topics

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