Iterating Von Neumann's post-processing under hardware constraints

@article{Rozic2016IteratingVN,
  title={Iterating Von Neumann's post-processing under hardware constraints},
  author={Vladimir Rozic and Bohan Yang and Wim Dehaene and Ingrid Verbauwhede},
  journal={2016 IEEE International Symposium on Hardware Oriented Security and Trust (HOST)},
  year={2016},
  pages={37-42}
}
In this paper we present a design methodology and hardware implementations of lightweight post-processing modules for debiasing random bit sequences. This work is based on the iterated Von Neumann procedure (IVN). We present a method to maximize the efficiency of IVN for applications with area and throughput constraints. The resulting hardware modules can be applied for post-processing raw numbers in random number generators.