Investigation of failures on dual-dies stacked package

  title={Investigation of failures on dual-dies stacked package},
  author={Yi Heng Chen and W. B. Lin and H. W. Huang and Meiying Hsiao and Chen-Hsien Ko},
  journal={Proceedings of the 20th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)},
The exploration for higher performance in memory has steered the industry towards dual-dies architectures which has significantly increased the challenges in silicon-package integration. In dual-dies package (DDP) technology is recommended to pack two semiconductor chips within one single package module. In our dual-die package use of a back-to-back die stacked configurations with two high-capacity DRAM chips in one single package module to enhance the performance of DRAM devices. During… CONTINUE READING


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