Investigation of Single pMOSFET Gate Oxide Degradation on NOR Logic Circuit Operability

@inproceedings{Estrada2007InvestigationOS,
  title={Investigation of Single pMOSFET Gate Oxide Degradation on NOR Logic Circuit Operability},
  author={David Estrada},
  year={2007}
}
The impact of gate oxide degradation of a single pMOSFET on the performance of the CMOS NOR logic circuit has been examined using a switch matrix technique. A constant voltage stress of -4.0V was used to induce a low level of degradation to the 2.0nm gate oxide of the pMOSFET. Characteristics of the CMOS NOR logic circuit following gate oxide degradation are analyzed in both the DC and V-t domains. The NOR gate rise time increases by approximately 30%, which may lead to timing or logic errors… CONTINUE READING

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