Investigation of Gate Underlap Design on Linearity of Operational Transconductance Amplifier (OTA)

Abstract

The significance of optimization of gate–source/drain extension region (also known as underlap design) in double gate (DG) silicon-on-insulator (SOI) FETs to improve the linearity performance of a low power folded cascode operational transconductance amplifier (OTA) is described. Based on a new figure-of-merit (FoM) involving AV , linearity, fT and dc power… (More)

Topics

7 Figures and Tables