Investigation of Gate Etch Damage at Metal/High-$k$ Gate Dielectric Stack Through Random Telegraph Noise in Gate Edge Direct Tunneling Current

@article{Cho2011InvestigationOG,
  title={Investigation of Gate Etch Damage at Metal/High-\$k\$  Gate Dielectric Stack Through Random Telegraph Noise in Gate Edge Direct Tunneling Current},
  author={Heung-Jae Cho and Y. Son and Byoungchan Oh and Seunghyun Jang and Jongho Lee and Byung-Gook Park and Hyungcheol Shin},
  journal={IEEE Electron Device Letters},
  year={2011},
  volume={32},
  pages={569-571}
}
Plasma damage on a high-k/SiO2 dielectric at a gate edge during a dry etch process is investigated. The damage was observed to generate slow oxide traps, causing a random telegraph noise (RTN) in a gate edge direct tunneling current. Through the analysis of the RTN, the distribution of the oxide traps in the high-k/SiO2 dielectric was obtained, and the plasma-damage-induced oxide traps were found to be distributed over a wide area of the high-k/SiO2 sidewall at the gate edge region. 

Figures from this paper

Defect properties of high-k/metal-gate metal–oxide–semiconductor field-effect transistors determined by characterization of random telegraph noise
The defect severity in n-channel high-k/metal-gate MOSFETs is analyzed with the trap energy level extracted from the random telegraph noise (RTN). The external factors of are the gate overdrive andExpand
Study of slow oxide trap creating random telegraph noise within a gate edge overlap region in inversion mode
We investigated a slow oxide trap causing a random telegraph noise (RTN) within a gate edge overlap region in an inversion mode at metal/high-k dielectric nMOSFETs. The oxide trap was observed toExpand
Investigation of Trap Properties in High-k/Metal Gate p-Type Metal–Oxide–Semiconductor Field-Effect Transistors with SiGe Source/Drain Using Random Telegraph Noise Analysis
The random telegraph noise (RTN) characteristics of high-k/metal gate (HK/MG) p-type metal–oxide–semiconductor field-effect transistors (pMOSFETs) with SiGe source/drain (SiGe S/D) have beenExpand
Impact of Uniaxial Strain on Random Telegraph Noise in High- $k$ /Metal Gate pMOSFETs
The random telegraph noise (RTN) characteristics of high-k (HK)/metal gate (MG) pMOSFETs with uniaxial compressive strain have been investigated. The configuration-coordinate diagram and band diagramExpand
Comparison of electrical characteristics for SiONx and HfZrOx gate dielectrics of MOSFETs with decoupled plasma nitridation treatment
Display Omitted The gate leakage with oxynitride dielectric around 1.5nm thickness was sensed.The gate leakage with HfZrOx dielectric around 1.5nm thickness was extracted.The ON currents for bothExpand
Plasma Charging Damage in HK-First and HK-Last RMG NMOS Devices
This work reports on charging damage induced by gate antennae in high- $\kappa $ (HK) Replacement Metal Gate (RMG) technology for the HK-first and HK-last integration flows, comparing plate and combExpand
Correlation Between Random Telegraph Noise and $ \hbox{1}/f$ Noise Parameters in 28-nm pMOSFETs With Tip-Shaped SiGe Source/Drain
The random telegraph noise (RTN) characteristics of 28-nm pMOSFETs with tip-shaped SiGe source/drain have been investigated. RTN analysis found that strained devices undergo higher compressiveExpand
Extraction of Location and Energy Level of the Trap Causing Random Telegraph Noise at Reverse-Biased Region in GaN-Based Light-Emitting Diodes
In order to analyze the trap in the multi-quantum well (MQW) consisting of a GaN-InGaN pair, the extraction of the location and energy level of the trap using random-telegraph-noise experiment wasExpand
A Statistical Model for the Headed and Tail Distributions of Random Telegraph Signal Magnitudes in Nanoscale MOSFETs
Trapping-detrapping of a single electron via an individual trap in metal-oxide-semiconductor field-effect transistor (MOSFET) gate dielectric constitutes two-level random telegraph signals. RecentExpand
Characterization of Random Telegraph Noise Generated by Process- and Cycling-Stress-Induced Traps in 26 nm NAND Flash Memory (Special Issue : Solid State Devices and Materials)
We characterized normalized noise power density (SI/IBL2) and bit-line (BL) current fluctuation (ΔIBL) using traps generated applying cycling stress in 26 nm NAND flash memory. The ΔIBL, SI/IBL2, andExpand
...
1
2
...

References

SHOWING 1-10 OF 15 REFERENCES
The observation of trapping and detrapping effects in high-k gate dielectric MOSFETs by a new gate current Random Telegraph Noise (IG-RTN) approach
A new method, called gate current random telegraph noise (IG RTN), was developed to analyze the oxide quality and reliability of high-k gate dielectric MOSFETs. First, a single electronExpand
Study on Time Constants of Random Telegraph Noise in Gate Leakage Current Through Hot-Carrier Stress Test
Capture and emission time constants obtained from random telegraph noise in gate leakage current ( Ig RTN) are studied by characterizing an intentionally created trap in thin gate oxide (2.6 nm) inExpand
Characterization of oxide traps leading to RTN in high-k and metal gate MOSFETs
We proposed a new method for characterization of oxide traps leading to Random Telegraph Noise (RTN) in high-k and metal gate MOSFETs considering their energy band structure. Through this method andExpand
Investigation of Random Telegraph Noise in Gate-Induced Drain Leakage and Gate Edge Direct Tunneling Currents of High-$k$ MOSFETs
Random telegraph noise (RTN) in gate-induced drain leakage (GIDL) and gate edge direct tunneling (EDT) leakage currents under GIDL bias conditions were characterized in MOSFETs with a high-k gateExpand
Extraction of trap energy and location from random telegraph noise in gate leakage current (Ig RTN) of metal–oxide semiconductor field effect transistor (MOSFET)
Abstract Study of random telegraph noise in gate leakage current ( I g RTN) through thin gate oxide (2.6 nm) as well as drain current random telegraph noise ( I d RTN) has been conducted in MOSFET.Expand
A novel in situ plasma treatment for damage-free metal/high-k gate stack RIE process
A dry etch process for metal/high-k stacks has been developed to solve the integration problems associated with wet etch removal of high-k dielectric from the source and drain (S/D) areas. An in-situExpand
A novel damage-free high-k etch technique using neutral beam-assisted atomic layer etching (NBALE) for sub-32nm technology node low power metal gate/high-k dielectric CMOSFETs
  • K. Min, C. Kang, +10 authors G. Yeom
  • Materials Science
  • 2009 IEEE International Electron Devices Meeting (IEDM)
  • 2009
For the first time, a novel damage-free neutral beam-assisted atomic etching process has successfully demonstrated the removal of the residual high-k dielectric layer after gate patterning. Due toExpand
Plasma-Process-Induced Damage in Sputtered TiN Metal-Gate Capacitors with Ultrathin Nitrided Oxides
A comprehensive study on plasma-process-induced damage (P2ID) in sputtered TiN metal-gated devices with 4 nm N2O-nitrided oxide was performed. We found that the TiN metal-gated devices exhibit aExpand
Oxide-trap-enhanced Coulomb energy in a metal-oxide-semiconductor system
Coulomb energy is essential to the charging of a nanometer-scale trap in the oxide of a metal-oxide-semiconductor system. Traditionally the Coulomb energy calculation was performed on the basis of anExpand
1/f Noise Characteristics of Sub-100 nm MOS Transistors
We report 1/f noise PSD(Power Spectrum Density) of sub-100 nm MOSFETs as a function of various parameters such as HCS (Hot Carrier Stress), bias condition, temperature, device size and types ofExpand
...
1
2
...