Interfacing synchronous and asynchronous modules within a high-speed pipeline

Abstract

This paper describes a new technique for integrating asynchronous modules within a high-speed synchronous pipeline. Our design eliminates potential metastability problems by using a clock generated by a stoppable ring oscillator, which is capable of driving the large clock load found in present day microprocessors. Using the ATACS design tool, we designed highly optimized transistor-level circuits to control the ring oscillator and generate the clock and handshake signals with minimal overhead. Our interface architecture requires no redesign of the synchronous circuitry. Incorporating asyn-chronous modules in a high-speed pipeline improves performance by exploiting data-dependent delay variations. Since the speed of the synchronous circuitry tracks the speed of the ring oscillator under diierent processes, temperatures, and voltages, the entire chip operates at the speed dictated by the current operating conditions, rather than being governed by the worst-case conditions. These two factors together can lead to a signiicant improvement in average-case performance. The interface design is tested using the 0:6m HP CMOS14B process in HSPICE. Circuit designers are continually pushing the envelope in the race to design faster, more powerful microprocessors. Present day synchronous microprocessors have clock speeds in excess of 300MHz. Distributing a clock signal to all areas of a large chip at this speed with minimal clock skew is a task of growing complexity. The circuit area, power consumption, and design time needed to drive the clock signal to all parts of the chip without signiicant clock skew are overwhelming 4, 1]. The clock period must also be long enough to accommodate the worst-case delay in every module in the worst process run under the highest temperature and lowest supply voltage. Thus, any speed gained from completing an operation early is lost waiting for the clock, which runs at a rate dictated by the slowest component running in the worst operating conditions. Asynchronous circuits have attracted new interest as an alternative to synchronous circuits due to their potential to achieve average-case performance while eliminating the global synchronizing clock signal. In asynchronous circuits, an operation begins when all the operations that it depends on have occurred, rather than when the next clock signal arrives. This allows asynchronous circuits to operate as fast as possible, taking advantage of delay variations due to data dependencies and operating conditions. Thus, well-designed asynchronous circuits can achieve better average operating frequencies than synchronous circuits operating at frequencies dictated by the worst-case conditions. Asynchronous circuits also eliminate the …

DOI: 10.1109/92.894162

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@article{Sjogren1997InterfacingSA, title={Interfacing synchronous and asynchronous modules within a high-speed pipeline}, author={Allen E. Sjogren and Chris J. Myers}, journal={IEEE Trans. VLSI Syst.}, year={1997}, volume={8}, pages={573-583} }