Interests and Limitations of Technology Scaling for Subthreshold Logic

@article{Bol2009InterestsAL,
  title={Interests and Limitations of Technology Scaling for Subthreshold Logic},
  author={David Bol and Renaud Ambroise and Denis Flandre and Jean-Didier Legat},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2009},
  volume={17},
  pages={1508-1519}
}
Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. In this paper, the interests and limitations of technology scaling for subthreshold logic are investigated from 0.25 mum to 32 nm nodes. Scaling to 90/65 nm nodes is shown to be highly desirable for medium-throughput applications (1-10 MHz) due to great dynamic energy reduction. However, this interest is limited at 45/32 nm nodes by high static energy due to degraded… CONTINUE READING
Highly Cited
This paper has 163 citations. REVIEW CITATIONS

18 Figures & Tables

Topics

Statistics

020402009201020112012201320142015201620172018
Citations per Year

163 Citations

Semantic Scholar estimates that this publication has 163 citations based on the available data.

See our FAQ for additional information.