Interests and Limitations of Technology Scaling for Subthreshold Logic

  title={Interests and Limitations of Technology Scaling for Subthreshold Logic},
  author={David Bol and Renaud Ambroise and Denis Flandre and Jean-Didier Legat},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
Subthreshold logic is an efficient technique to achieve ultralow energy per operation for low-to-medium throughput applications. In this paper, the interests and limitations of technology scaling for subthreshold logic are investigated from 0.25 mum to 32 nm nodes. Scaling to 90/65 nm nodes is shown to be highly desirable for medium-throughput applications (1-10 MHz) due to great dynamic energy reduction. However, this interest is limited at 45/32 nm nodes by high static energy due to degraded… CONTINUE READING
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