Interconnect-aware low-power high-level synthesis

@article{Zhong2005InterconnectawareLH,
  title={Interconnect-aware low-power high-level synthesis},
  author={Lin Zhong and Niraj Kumar Jha},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2005},
  volume={24},
  pages={336-351}
}
Interconnects (wires, buffers, clock distribution networks, multiplexers, and busses) consume a significant fraction of total circuit power. In this paper, we demonstrate the importance of optimizing on-chip interconnects for power during high-level synthesis. We present a methodology to integrate interconnect power optimization into high-level synthesis. It not only reduces datapath unit power consumption in the resultant register-transfer level architecture, but also optimizes interconnects… CONTINUE READING

Figures, Tables, Results, and Topics from this paper.

Key Quantitative Results

  • Compared with interconnect-unaware power-optimized circuits, interconnect power can be reduced by 53.1% on average, while overall power is reduced by an average of 26.8%, with negligible area overhead. Compared with area-optimized circuits, the interconnect power reduction is 72.9% and overall power reduction is 56.0%, with 44.4% area overhead.

Citations

Publications citing this paper.
SHOWING 1-10 OF 27 CITATIONS

References

Publications referenced by this paper.
SHOWING 1-10 OF 60 REFERENCES

Similar Papers

Loading similar papers…