Intelligent Robustness Insertion for Optimal Transient Error Tolerance Improvement in VLSI Circuits

Abstract

Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to radiation-induced single-event-upsets (SEUs). Redundancy insertion has been adopted to provide the circuit with additional transient error resiliency. However, its applicability and efficiency are limited by the tight design constraints and budgets. In this paper… (More)
DOI: 10.1109/TVLSI.2008.2000256

12 Figures and Tables

Topics

  • Presentations referencing similar topics