Integration verification across software and hardware for a simple embedded system

@article{Erbsen2021IntegrationVA,
  title={Integration verification across software and hardware for a simple embedded system},
  author={Andres Erbsen and Samuel Gruetter and Joonwon Choi and Clark Wood and A. Chlipala},
  journal={Proceedings of the 42nd ACM SIGPLAN International Conference on Programming Language Design and Implementation},
  year={2021}
}
The interfaces between layers of a system are susceptible to bugs if developers of adjacent layers proceed under subtly different assumptions. Formal verification of two layers against the same formal model of the interface between them can be used to shake out these bugs. Doing so for every interface in the system can, in principle, yield unparalleled assurance of the correctness and security of the system as a whole. However, there have been remarkably few efforts that carry out this exercise… Expand

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References

SHOWING 1-10 OF 63 REFERENCES
seL4: formal verification of an OS kernel
TLDR
To the knowledge, this is the first formal proof of functional correctness of a complete, general-purpose operating-system kernel. Expand
Verified compilation on a verified processor
TLDR
This paper shows how to extend the trustworthy development methodology of the CakeML project, including its verified compiler, with a connection to verified hardware, and results are an approach to producing verified stacks that scales to proving correctness, at the hardware level, of the execution of realistic software including compilers and proof checkers. Expand
The Verisoft Approach to Systems Verification
TLDR
The layers are discussed and the trade-off between efficiency of reasoning at a more abstract layer versus the development of meta-theory to transfer the verification results between the layers is discussed. Expand
Hyperkernel: Push-Button Verification of an OS Kernel
TLDR
Experience shows that Hyperkernel can avoid bugs similar to those found in xv6, and that the verification of Hyper kernel can be achieved with a low proof burden. Expand
Kami: a platform for high-level parametric hardware specification and its modular verification
TLDR
Kami is introduced, a Coq library that enables similar expressive and modular reasoning for hardware designs expressed in the style of the Bluespec language, and can specify, implement, and verify realistic designs entirely within Coq, ending with automatic extraction into a pipeline that bottoms out in FPGAs. Expand
Formal Device and Programming Model for a Serial Interface
TLDR
This paper presents the formal model of the serial interface controller UART 16550A, an assembler-level programming model for a serial interface that has been formally specified in the Isabelle/HOL theorem prover. Expand
A Multipurpose Formal RISC-V Specification
TLDR
This work sets out to identify the commonalities between projects and to represent the RISC-V specification as a program with holes that can be instantiated differently by different projects, and to serve as the interface between a processor-correctness proof and a compiler-Correctness proof. Expand
Scaling symbolic evaluation for automated verification of systems code with Serval
This paper presents Serval, a framework for developing automated verifiers for systems software. Serval provides an extensible infrastructure for creating verifiers by lifting interpreters underExpand
Ironclad Apps: End-to-End Security via Automated Full-System Verification
TLDR
This work provides complete, low-level software verification of a full stack of verified software, which includes a verified kernel; verified drivers; verified system and crypto libraries including SHA, HMAC, and RSA; and four Ironclad Apps. Expand
Deep Specifications and Certified Abstraction Layers
TLDR
This paper presents a new layer calculus showing how to formally specify, program, verify, and compose abstraction layers and shows that they correspond to a strong form of abstraction over a particularly rich class of specifications which they call deep specifications. Expand
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4
5
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