Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques

Abstract

Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in overestimations owing to insu cient path and/or timing analysis. This paper presents a new method that integrates path and timing analysis to address these limitations. First, it is based… (More)
DOI: 10.1007/BFb0057776

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