Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques


Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in overestimations owing to insu cient path and/or timing analysis. This paper presents a new method that integrates path and timing analysis to address these limitations. First, it is based… (More)
DOI: 10.1007/BFb0057776


2 Figures and Tables


Citations per Year

101 Citations

Semantic Scholar estimates that this publication has 101 citations based on the available data.

See our FAQ for additional information.

Slides referencing similar topics