Instruction Prefetching of Systems Codes with Layout Optimized for Reduced Cache Misses

  title={Instruction Prefetching of Systems Codes with Layout Optimized for Reduced Cache Misses},
  author={Josep Torrellas and Chun Xia},
  journal={23rd Annual International Symposium on Computer Architecture (ISCA'96)},
High-performing on-chip instruction caches are crucial to keep fast processors busy. Unfortunately, while on-chip caches are usually successful at intercepting instruction fetches in loop-intensive engineering codes, they are less able to do so in large systems codes. To improve the performance of the latter codes, the compiler can be used to lay out the code in memory for reduced cache conflicts. Interestingly, such an operation leaves the code in a state that can be exploited by a new type of… CONTINUE READING
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