Corpus ID: 215836424

Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers

@article{SohiGurindar1990InstructionIL,
  title={Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers},
  author={S. SohiGurindar},
  journal={IEEE Transactions on Computers},
  year={1990}
}
  • S. SohiGurindar
  • Published 1990
  • Computer Science
  • IEEE Transactions on Computers
  • The problems of data dependency resolution and precise interrupt implementation in pipelined processors are combined. A design for a hardware mechanism that resolves dependencies dynamically and, a... 
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