Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers
@article{SohiGurindar1990InstructionIL,
title={Instruction Issue Logic for High-Performance, Interruptible, Multiple Functional Unit, Pipelined Computers},
author={S. SohiGurindar},
journal={IEEE Transactions on Computers},
year={1990}
}The problems of data dependency resolution and precise interrupt implementation in pipelined processors are combined. A design for a hardware mechanism that resolves dependencies dynamically and, a...
Topics from this paper
200 Citations
A fill-unit approach to multiple instruction issue
- Computer Science
- Proceedings of MICRO-27. The 27th Annual IEEE/ACM International Symposium on Microarchitecture
- 1994
- 67
- PDF
In-cache pre-processing and decode mechanisms for fine grain parallelism in SCISM
- Computer Science
- Proceedings of Phoenix Conference on Computers and Communications
- 1993
- 2
An out-of-order superscalar processor with speculative execution and fast, precise interrupts
- Chemistry, Computer Science
- MICRO 25
- 1992
- 25
- PDF
OHMEGA : a VLSI superscalar processor architecture for numerical applications
- Computer Science
- [1991] Proceedings. The 18th Annual International Symposium on Computer Architecture
- 1991
- 8
- PDF
Zero-cycle loads: microarchitecture support for reducing load latency
- Computer Science
- Proceedings of the 28th Annual International Symposium on Microarchitecture
- 1995
- 89
- PDF
An architectural framework for supporting heterogeneous instruction-set architectures
- Computer Science
- Computer
- 1993
- 70
- PDF