Instruction Cache Locking Using Temporal Reuse Profile

  title={Instruction Cache Locking Using Temporal Reuse Profile},
  author={Yun Liang and Tulika Mitra},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
The performance of most embedded systems is critically dependent on the average memory access latency. Improving the cache hit rate can have significant positive impact on the performance of an application. Modern embedded processors often feature cache locking mechanisms that allow memory blocks to be locked in the cache under software control. Cache locking was primarily designed to offer timing predictability for hard real-time applications. Hence, the compiler optimization techniques focus… CONTINUE READING
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