• Corpus ID: 244908496

Insights into Cold Source MOSFETs with Sub-60 mV/decade and Negative Differential Resistance Effect

@inproceedings{Yin2021InsightsIC,
  title={Insights into Cold Source MOSFETs with Sub-60 mV/decade and Negative Differential Resistance Effect},
  author={Yiheng Yin and Zhaofu Zhang and Chen Shao and John Robertson and Yuzheng Guo},
  year={2021}
}
To extend the Moore’s law in the 5 nm node, a large number of two dimensional (2D) materials and devices have been thoroughly researched, among which the “cold” metals 2H MS2 (M = Nb, Ta) with unique band structures are expected to achieve the sub-60 mV/dec subthreshold swing (SS). The studied “cold” metal field-effect transistors (CM-FETs) based on the “cold” metals are capable to fulfill the high-performance (HP) and low-dissipation (LP) goals simultaneously, as required by the International… 

Figures from this paper

References

SHOWING 1-9 OF 9 REFERENCES

Sub-5nm All-Around Gate FinFET for Ultimate Scaling

Sub-5nm all-around gate FinFETs with 3nm fin width were fabricated for the first time. The n-channel FinFET of sub-5nm with 1.4nm HfO2 shows an IDsat of 497muA/mum at VG=V D=1.0V. Characteristics of

First Principles Simulation of Energy efficient Switching by Source Density of States Engineering

Achieving sub-60 mV/decade FET switching is critical for reducing power dissipation in integrated circuits. Here we propose and theoretically investigate steep slope switching made possible by a

5nm CMOS Production Technology Platform featuring full-fledged EUV, and High Mobility Channel FinFETs with densest 0.021µm2 SRAM cells for Mobile SoC and High Performance Computing Applications

  • G. YeapX. Chen M. Wang
  • Computer Science, Engineering
    2019 IEEE International Electron Devices Meeting (IEDM)
  • 2019
The 5nm platform technology successfully passed qualification with consistently high yielding 256Mb HD/HC SRAM, and large logic test chip consisting of CPU/GPU/SoC blocks, on schedule for high volume production in 1H 2020.

More Moore landscape for system readiness - ITRS2.0 requirements

This paper covers a portfolio of More Moore technologies for power-aware device enabling value proposition for system scaling - where requirements and gaps will be addressed in the ITRS2.0 roadmap.

Quantum Transport: Atom to Transistor

Foreword 1. Prologue - electrical resistance: an atomistic view 2. Schrodinger equation 3. Self-consistent field 4. Basis functions 5. Bandstructure 6. Subbands 7. Capacitance 8. Level broadening 9.

“ More-than-Moore ” White Paper

Since its inception in 1998, the objective of the International Technology Roadmap for Semiconductors (ITRS) has been to identify the technical challenges that had to be addressed in order to ensure

5 nm CMOS Production Technology Platform Featuring Full-Fledged EUV

  • and High Mobility Channel FinFETs with Densest 0.021 μm 2 SRAM Cells for Mobile SoC and High Performance Computing Applications", presented at 2019 IEEE International Electron Devices Meeting (IEDM)
  • 2019

22 nm FDSOI Technology for Emerging Mobile, Internet-of-Things, and RF Applications

  • 2016 IEEE International Electron Devices Meeting (IEDM)
  • 2016

22 nm FDSOI Technology for Emerging Mobile

  • Internet-of-Things, and RF Applications", presented at 2016 IEEE International Electron Devices Meeting (IEDM)
  • 2016