Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications

@article{Chan2008InsertionLA,
  title={Insertion loss analysis in a photonic interconnection network for on-chip and off-chip communications},
  author={Johnnie Chan and Aleksandr Biberman and B. G. Lee and Keren Bergman},
  journal={LEOS 2008 - 21st Annual Meeting of the IEEE Lasers and Electro-Optics Society},
  year={2008},
  pages={300-301}
}
An on-chip photonic interconnection network is simulated to determine statistical insertion losses for different network sizes and non-blocking switch layouts. For an 8times8 folded-torus network, we obtain an optical link loss budget of 15.5 dB. 
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An insertion loss balance aware routing scheme in photonic network on chip

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