Input Vector Reordering for Leakage Power Reduction in FPGAs

@article{Hassan2008InputVR,
  title={Input Vector Reordering for Leakage Power Reduction in FPGAs},
  author={Hassan Hassan and Mohab Anis and Mohamed I. Elmasry},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
  year={2008},
  volume={27},
  pages={1555-1564}
}
In this paper, a leakage power reduction technique for field-programmable gate arrays (FPGAs) is proposed based on the state dependency property of leakage power. A pin reordering algorithm is proposed, where the subthreshold and gate leakage power components are taken into consideration to find the lowest leakage state for the FPGA pass-transistor multiplexers in the logic and routing resources without incurring any physical or performance penalties. The newly developed methodology is applied… CONTINUE READING