Corpus ID: 16516100

Input-Output Logic based Fault-Tolerant Design Technique for SRAM-based FPGAs

@article{Timmaraju2013InputOutputLB,
  title={Input-Output Logic based Fault-Tolerant Design Technique for SRAM-based FPGAs},
  author={A. Timmaraju and A. Deshmukh and Mohammed Amir Khan and Zafar Ali Khan},
  journal={ArXiv},
  year={2013},
  volume={abs/1311.0602}
}
Effects of radiation on electronic circuits used in extra-terrestrial applications and radiation prone environments need to be corrected. Since FPGAs offer flexibility, the effects of radiation on them need to be studied and robust methods of fault tolerance need to be devised. In this paper a new fault-tolerant design strategy has been presented. This strategy exploits the relation between changes in inputs and the expected change in output. Essentially, it predicts whether or not a change in… Expand

References

SHOWING 1-10 OF 29 REFERENCES
On the optimal design of triple modular redundancy logic for SRAM-based FPGAs
TLDR
The experimental results presented in this paper demonstrate that the number and placement of voters in the TMR design can directly affect the fault tolerance, ranging from 4.03% to 0.98% the number of upsets in the routing able to cause an error in theTMR circuit. Expand
Analysis of the robustness of the TMR architecture in SRAM-based FPGAs
Non radiation-hardened SRAM-based Field Programmable Gate Arrays (FPGAs) are very sensitive to Single Event Upsets (SEUs) affecting their configuration memory and thus suitable hardening techniquesExpand
Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs
TLDR
The power and area analysis of the proposed techniques show that these methods are more efficient than the traditional schemes such as duplication with comparison and TMR circuit design in the FPGAs. Expand
Radiation Test Results of the Virtex FPGA and ZBT SRAM for Space Based Reconfigurable Computing
A comprehensive Single Event Effects (SEE) characterization of advanced commercial technologies was conducted using the heavy-ion test facility at Texas A&M. The components evaluated included aExpand
CRC circuit design for SRAM-Based FPGA configuration bit correction
TLDR
In this paper, the existing techniques for SEU mitigation are introduced, and their shortcomings are pointed out, and a new mitigation algorithm is proposed that is both feasible and effective. Expand
Designing fault-tolerant techniques for SRAM-based FPGAs
TLDR
A fault tolerance technique for transient and permanent faults in SRAM-based FPGAs is presented that combines duplication with comparison and concurrent error detection to provide a highly reliable circuit while maintaining hardware, pin, and power overheads far lower than with classic triple-modular-redundancy techniques. Expand
Improving the Reliability of a FPGA Using Fault-Tolerance Mechanism Based on Magnetic Memory (MRAM)
TLDR
The present work proposes an approach to improve the reliability of the FPGAs, regarding SEU events at ground level for the future submicronic scale technologies proposing the adoption of Magnetic Random Access Memories (MRAMs) cells into a simple fault-tolerant system for FPGA manufactured below 65nm submicronics scale. Expand
Soft error mitigation for SRAM-based FPGAs
  • H. Asadi, M. Tahoori
  • Engineering, Computer Science
  • 23rd IEEE VLSI Test Symposium (VTS'05)
  • 2005
TLDR
Experimental results show that, using a high-reliable low-cost mitigation technique, the availability of an FPGA mapped design can be increases to more than 99%. Expand
Synthetical analysis on space radiation tolerance techniques in ASICs and FPGAs
  • Shangqing Zhang, Hongjin Liu
  • Engineering
  • 2011 International Conference on System science, Engineering design and Manufacturing informatization
  • 2011
The space radiation environment introduces multiple kinds of faults on devices used for space application. Advantages and shortages of ASIC and FPGA are compared based on different radiation effects.Expand
Detecting SEU-caused routing errors in SRAM-based FPGAs
TLDR
A new CLB architecture for FPGAs and an associated testing technique that detects routing errors caused by SEUs in the SRAM configuration memory of the FPGA is proposed and it is noteworthy that the time required for error detection is independent of both the number of switch matrices and thenumber of logic blocks in the FPN. Expand
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