Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis

  title={Input Capacitance Modeling of Logic Gates for Accurate Static Timing Analysis},
  author={Takeshi Kouno and Masanori Hashimoto and Hidetoshi Onodera},
  journal={2005 IEEE Asian Solid-State Circuits Conference},
This paper discusses how to improve input capacitance modeling of logic gates for accurate STA (static timing analysis). The input capacitance of logic gates exhibits nonlinear behavior with respect to input signal voltage. Also, its value varies depending on the driving condition of stable inputs as well as loading of multiple-input gates condition of the gate. For the non-linearity issue, the authors propose to use an equivalent capacitance value derived by the integration of input current… CONTINUE READING
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