Influence of gate length on ESD-performance for deep sub micron CMOS technology

@article{Bock1999InfluenceOG,
  title={Influence of gate length on ESD-performance for deep sub micron CMOS technology},
  author={Karlheinz Bock and Bart Keppens and Vincent De Heyn and Guido Groeseneken and L. Y. Ching and A. Naem},
  journal={Electrical Overstress/Electrostatic Discharge Symposium Proceedings. 1999 (IEEE Cat. No.99TH8396)},
  year={1999},
  pages={95-104}
}
The ESD performance of grounded-gate nMOS protection structures has been observed for a standard 0.25 /spl mu/m CMOS epitaxial layer based technology. The shortest gate lengths show unexpectedly lower ESD thresholds, leading to an optimum performance for longer gate length devices attributed to the trade-off between power dissipation and melt volume of the parasitic bipolar device. 
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