Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories

@inproceedings{Yasufuku2009InductorDO,
  title={Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories},
  author={Tadashi Yasufuku and Koichi Ishida and Shinji Miyamoto and Hiroto Nakai and Makoto Takamiya and Takayasu Sakurai and Ken Takeuchi},
  booktitle={ISLPED},
  year={2009}
}
A 3D-integrated Solid State Drive (SSD) with the boost converter can achieve both the low power and the fast write-operation at the small die area of the NAND flash memory. The performance of the boost converter, however, is critically affected by the inductor, because the output voltage of the boost converter, the rising time, and the energy consumption during the boost are determined by the inductor. Therefore, this paper proposes a design methodology of the inductor of the boost converter… 
Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories
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Two essential technologies for a 3D Solid State Drive (3D-SSD) with a boost converter are presented in this paper, the spiral inductor design which determines the performance of the boost converter, and the effect of TSV's on the boosted converter.
PAPER Special Section on Circuits and Design Techniques for Advanced Large Scale Integration Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories
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References

SHOWING 1-10 OF 19 REFERENCES
A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD
  • K. Ishida, T. Yasufuku, +4 authors K. Takeuchi
  • Engineering, Computer Science
    2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers
  • 2009
TLDR
A low-power program-voltage generator (PVG) is implemented using a boost converter with an adaptive-frequency and duty-cycle (AFD) controller to reduce power consumption of SSDs.
Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories
TLDR
This paper investigates the effect of the TSV resistance (R<inf>TSV</inf>) on the performance of boost converters for Solid State Drive (SSD) using circuit simulation and finds that the reduction of R<inf*TSV* is very important.
Novel Co-Design of NAND Flash Memory and NAND Flash Controller Circuits for Sub-30 nm Low-Power High-Speed Solid-State Drives (SSD)
  • K. Takeuchi
  • Computer Science
    IEEE Journal of Solid-State Circuits
  • 2009
TLDR
Three new circuit technologies, the selective bit-line precharge scheme, the advanced source-line program, and the intelligent interleaving, are proposed, which reduce the current consumption of the NAND flash memory and the SSD speed improves by 150% without a cost penalty or circuit noise.
A 120mm2 16Gb 4-MLC NAND Flash Memory with 43nm CMOS Technology
  • K. Kanda, M. Koyanagi, +34 authors S. Ohshima
  • Engineering, Computer Science
    2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers
  • 2008
TLDR
A 16 Gb 4-level NAND flash memory in 43 nm CMOS technology is developed to meet the stringent requirements, and two dummy wordlines on both sides of NAND strings are added to avoid GIDL.
Novel co-design of NAND flash memory and NAND flash controller circuits for sub-30nm low-power high-speed solid-state drives (SSD)
  • K. Takeuchi
  • Computer Science
    2008 IEEE Symposium on VLSI Circuits
  • 2008
TLDR
Three new circuit technologies, selective bit-line precharge scheme, advanced source-line program, and intelligent interleaving are proposed by co-designing NAND flash memory and NAND controller circuits, which improve SSD speed by 150% without a cost penalty or circuit noise.
Numerical state-space average-value modeling of PWM DC-DC converters operating in DCM and CCM
State-space average-value modeling of pulsewidth modulation converters in continuous and discontinuous modes has received significant attention in the literature, and various models have been
Three-Dimensional Packaging Technology for Stacked DRAM With 3-Gb/s Data Transfer
A 3-D packaging technology is developed for stacked dynamic random access memory (DRAM) with through-silicon vias (TSVs). Eight different dry etchers were evaluated for deep Si etching. Highly doped
Averaged modeling of PWM converters operating in discontinuous conduction mode
Various aspects of averaged modeling of hard-switching pulse-width modulated (PWM) converters operating in the discontinuous conduction mode (DCM) are studied. A more streamlined modeling procedure
Development and Evaluation of 3-D SiP with Vertically Interconnected Through Silicon Vias (TSV)
  • D. Jang, Chunghyun Ryu, +5 authors Jin Yu
  • Materials Science
    2007 Proceedings 57th Electronic Components and Technology Conference
  • 2007
For high density and performance of microelectronic devices, the 3-D system in package (SiP) has been considered as a superb microelectronic packaging system. The development and evaluation of
A 56nm CMOS 99mm2 8Gb Multi-level NAND Flash Memory with 10MB/s Program Throughput
  • K. Takeuchi, Y. Kameda, +32 authors S. Ohshima
  • Computer Science
    2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers
  • 2006
TLDR
The 10MB/s programming and 93ms block copy are realized by introducing 8kB page, noise-cancellation circuits, external page copy and the dual VDD scheme enabling efficient use of 1MB blocks.
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