Independent-gate and tied-gate FinFET SRAM Circuits: Design guidelines for reduced area and enhanced stability

@article{Tawfik2007IndependentgateAT,
  title={Independent-gate and tied-gate FinFET SRAM Circuits: Design guidelines for reduced area and enhanced stability},
  author={S. Tawfik and Zhiyu Liu and Volkan Kursun},
  journal={2007 Internatonal Conference on Microelectronics},
  year={2007},
  pages={171-174}
}
Data stability of static random access memory (SRAM) circuits has become an important issue with the scaling of CMOS technology. Memory arrays are also an important source of leakage since the majority of transistors are utilized for on-chip caches in today's high performance microprocessors. Two six transistor SRAM cells based on independent-gate FinFET technology (IG-FinFET) are described in this paper for simultaneously reducing the active and standby mode power consumption while enhancing… CONTINUE READING
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A Comparative Study of 6T and 4T SRAM Cells in Double-Gate CMOS with Statistical Variation

  • B. Giraud
  • Proceedings of the IEEE International Symposium…
  • 2007
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