Incremental retiming for FPGA physical synthesis

  title={Incremental retiming for FPGA physical synthesis},
  author={D. Singh and V. Manohararajah and S. Brown},
  journal={Proceedings. 42nd Design Automation Conference, 2005.},
In this paper, the authors presented a new linear-time retiming algorithm that produces near-optimal results. The implementation is specifically targeted at Altera's Stratix FPGA-based designs, although the techniques described are general enough for any implementation medium. The algorithm is able to handle the architectural constraints of the target device, multiple timing constraints assigned by the user and implicit legality constraints. It ensures that register moves do not create… Expand
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