Incremental retiming for FPGA physical synthesis

@article{Singh2005IncrementalRF,
  title={Incremental retiming for FPGA physical synthesis},
  author={D. Singh and V. Manohararajah and S. Brown},
  journal={Proceedings. 42nd Design Automation Conference, 2005.},
  year={2005},
  pages={433-438}
}
In this paper, the authors presented a new linear-time retiming algorithm that produces near-optimal results. The implementation is specifically targeted at Altera's Stratix FPGA-based designs, although the techniques described are general enough for any implementation medium. The algorithm is able to handle the architectural constraints of the target device, multiple timing constraints assigned by the user and implicit legality constraints. It ensures that register moves do not create… Expand
32 Citations
Two-stage physical synthesis for FPGAs
  • 13
  • PDF
Integrating Logic Synthesis, Technology Mapping, and Retiming
  • 28
  • PDF
Minimum-Perturbation Retiming for Delay Optimization
  • 2
  • PDF
Scalable min-register retiming under timing and initializability constraints
  • 10
  • PDF
Incremental Placement for Layout-Driven Logic Synthesis for Timing Closure
  • PDF
Latch-Based Performance Optimization for FPGAs
  • Bill Teng, J. Anderson
  • Computer Science
  • 2011 21st International Conference on Field Programmable Logic and Applications
  • 2011
  • 9
  • PDF
Supporting high-performance pipelined computation in commodity-style fpgas
  • 2
  • Highly Influenced
  • PDF
...
1
2
3
4
...

References

Smart move: a placement-aware retiming and replication method for field programmable gate arrays
  • 5
  • Highly Influential