Incremental logic rectification

@inproceedings{Huang1997IncrementalLR,
  title={Incremental logic rectification},
  author={Shi-Yu Huang and Kuang-Chien Chen and Kwang-Ting Cheng},
  booktitle={VTS},
  year={1997}
}
We address the problem of rectifying an incorrect combinational circuit against a given specification. Based on the symbolic BDD techniques, we consider the rectification process, as a sequence of partial corrections. Each partial correctiion reduces the size of the input vector set producing error responses. Compared with existing approaches, this approach is more general, and able to handle circuits with multiple errors. We also formulate the necessary and sufficient condition of general… CONTINUE READING
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Multi - level logic optimization by redundancy addition and removal

  • A. Drumm D. Brand, S. Kundu, P. Narrain, Cheng, A. Entrena L
  • 1993

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