Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits

  title={Incremental SAT-Based Reverse Engineering of Camouflaged Logic Circuits},
  author={Cunxi Yu and Xiangyu Zhang and Duo Liu and Maciej J. Ciesielski and Daniel Holcomb},
  journal={IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems},
Layout-level gate or routing camouflaging techniques have attracted interest as countermeasures against reverse engineering of combinational logic. In order to minimize area overhead, typically only a subset of gate or routing components are camouflaged, and each camouflaged component layout can implement one of a few different functions or connections. The security of camouflaging relies on the difficulty of learning the overall combinational logic function without knowing the functions… CONTINUE READING


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