A rc h i t e c t u re Specification: Version 1.1
- V. Kathail, M. Schlansker, B. R. Rau, H P L - P D
- Tech. Report HPL-93-80 (R.1),
O ver the past two and a half decades, the computer industry has grown accustomed to the spectacular rate of i n c rease in micro p rocessor perf o rmance. The industry accomplished this without fundamentally rewriting programs in a parallel form, without changing algorithms or languages, and often without even recompiling programs. For the time being at least, instruction-level parallel processing has established itself as the only viable approach for achieving higher performance without major changes to software. H o w e v e r, computers have thus far achieved this goal at the expense of tremendous hard w a re complexity— a complexity that has grown so large as to challenge the industry ’s ability to deliver ever-higher perf o rmance. This is why we developed the Explicitly Parallel I n s t ruction Computing (EPIC) style of arc h i t e c t u re: to enable higher levels of instruction-level parallelism without unacceptable hard w a re complexity.