Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures

Abstract

With the shift towards deep sub-micron (DSM) technologies, the increase in leakage power and the adoption of power-aware design methodologies have resulted in potentially significant variations in power consumption under different process, voltage and temperature (PVT) corners. In this paper, we first investigate the impact of PVT corners on power… (More)
DOI: 10.1109/VLSI.2008.14

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@article{Pasricha2008IncorporatingPV, title={Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures}, author={Sudeep Pasricha and Young-Hwan Park and Fadi J. Kurdahi and Nikil D. Dutt}, journal={21st International Conference on VLSI Design (VLSID 2008)}, year={2008}, pages={363-370} }