In search of "Forever," continued transistor scaling one new material at a time

  title={In search of "Forever," continued transistor scaling one new material at a time},
  author={Scott E. Thompson and Robert S. Chau and Tahir Ghani and Kaizad R. Mistry and Sunit Tyagi and Mark T. Bohr},
  journal={IEEE Transactions on Semiconductor Manufacturing},
  • S. Thompson, R. Chau, M. Bohr
  • Published 14 February 2005
  • Engineering
  • IEEE Transactions on Semiconductor Manufacturing
This work looks at past, present, and future material changes for the metal-oxide-semiconductor field-effect transistor (MOSFET). It is shown that conventional planar bulk MOSFET channel length scaling, which has driven the industry for the last 40 years, is slowing. To continue Moore's law, new materials and structures are required. The first major material change to extend Moore's law is the use of SiGe at the 90-nm technology generation to incorporate significant levels of strain into the Si… 
A Review of Nanoscale Channel and Gate Engineered FINFETs for VLSI Mixed Signal Applications Using Zirconium-di-Oxide Dielectrics
In the past, most of the research and development efforts in the area of CMOS and IC’s are oriented towards reducing the power and increasing the gain of the circuits. While focusing the attention on
Limits of CMOS Technology Scaling and Technologies Beyond-CMOS
—The scaling of CMOS transistors has driven the tremendous growth of the semiconductor industry for the last four decades. However, most experts are saying CMOS is reaching its limits. This paper
Ultra Small SOI DG MOSFETs and RF MEMS Applications
The continuous scaling-down process of the channel length over the last four decades is reaching its limits in terms of gate oxide thickness, short channel effects and power consumptions, all the
Exploring new channel materials for nanoscale CMOS devices: A simulation approach
Rahman, Anisur. Ph.D., Purdue University, December, 2005. Exploring New Channel Materials for Nanoscale CMOS Devices: A Simulation Approach. Major Professor: Mark Lundstrom and Gerhard Klimeck. The
Influence of Block Oxide Width on a Silicon-on-Partial-Insulator Field-Effect Transistor
In this paper, the influence of block oxide width (WBO) variations on a newly designed 40-nm gate-length silicon-on-partial-insulator field-effect transistor with block oxide (bSPIFET) was
Investigation of threshold voltage variations in NMOS
As MOSFET is rigorously scaled down to meet the expected circuit evolution according to the Moore’s Law, the issue of threshold voltage (VTH) becoming more dominant in transistor operation. This
Architecture of source-drain cavity of a p-channel field effect transistor for embedding with epitaxial SiGe for enhanced performance
Increase in power consumption in field effect transistors has been curtailed in recent years by introduction of mechanical stress to achieve device speed gain over and above the traditional speed vs.
Advanced numerical modeling applied to current prediction in ultimate CMOS devices
A two-dimensional simulation tool (UTOXPP) based on physical models which makes use of state of the art C++ architecture and accounts for a complete and friendly GUI is presented as UTOXPP delivers reliable results for advanced nodes in a timely manner, being an excellent choice for the industrial daily use.


A 90-nm logic technology featuring strained-silicon
A leading-edge 90-nm technology with 1.2-nm physical gate oxide, 45-nm gate length, strained silicon, NiSi, seven layers of Cu interconnects, and low-/spl kappa/ CDO for high-performance dense logic
FinFET scaling to 10 nm gate length
While the selection of new "backbone" device structure in the era of post-planar CMOS is open to a few candidates, FinFET and its variants show great potential in scalability and manufacturability
Evolution of the MOS transistor-from conception to VLSI
Historical developments of the metal-oxide-semiconductor field-effect transistor (MOSFET) during the last 60 years are reviewed, from the 1928 patent disclosures of the field-effect conductivity
Device scaling limits of Si MOSFETs and their application dependencies
The end result is that there is no single end point for scaling, but that instead there are many end points, each optimally adapted to its particular applications.
High performance fully-depleted tri-gate CMOS transistors
Fully-depleted (FD) tri-gate CMOS transistors with 60 nm physical gate lengths on SOI substrates have been fabricated. These devices consist of a top and two side gates on an insulating layer. The
A logic nanotechnology featuring strained-silicon
Strained-silicon (Si) is incorporated into a leading edge 90-nm logic technology . Strained-Si increases saturated n-type and p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) drive
Scaling fully depleted SOI CMOS
Quasi-two-dimensional (2-D) device analyses, 2-D numerical device simulations, and circuit simulations of nanoscale conventional, single-gate fully depleted (FD) silicon-on-insulator (SOI) CMOS are
CMOS scaling beyond 0.1 /spl mu/m: how far can it go?
  • Y. Taur
  • Engineering
    1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453)
  • 1999
This paper discusses the issues, challenges, and possible directions for further scaling and performance gains beyond 0.1 /spl mu/m CMOS. Gate oxides, already down to a few atomic layers thick, will
CMOS design near the limit of scaling
Beginning with a brief review of CMOS scaling trends from 1 µm to 0.1 µm, this paper examines the fundamental factors that will ultimately limit CMOS scaling and considers the design issues near the