In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis

@article{You2013InSituMF,
  title={In-Situ Method for TSV Delay Testing and Characterization Using Input Sensitivity Analysis},
  author={Jhih-Wei You and Shi-Yu Huang and Yu-Hsiang Lin and Meng-Hsiu Tsai and Ding-Ming Kwai and Yung-Fa Chou and Cheng-Wen Wu},
  journal={IEEE Transactions on Very Large Scale Integration (VLSI) Systems},
  year={2013},
  volume={21},
  pages={443-453}
}
In this paper, we propose a method and the required architecture for characterizing the propagation delays of the through Silicon vias (TSVs) in a 3-D IC. First of all, every two TSVs are paired up to form an oscillation ring with some peripheral circuits. Their joint performance can thus be measured roughly by the oscillation period of the ring. Next, we utilize a technique called sensitivity analysis to further derive the propagation delay of each individual TSV participating in an… CONTINUE READING

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