• Corpus ID: 196123316

In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers

@article{Naik2017InFieldTF,
  title={In-Field Test for Permanent Faults in FIFO Buffers of NoC Routers},
  author={Dhanavath Kiran Kumar Naik},
  journal={International Journal of Research},
  year={2017},
  volume={4},
  pages={2722-2726}
}
The Network-on-Chip (NoC) communication architecture is a packet based network where cores communicate among themselves by sending and receiving packets. High parallelism, smaller latency in data transmission and facility of Intellectual Property (IP) re-use have made NoCs overcome the problem of bandwidth and latency in conventional bus-based interconnects. In this concise proposes an on-line straightforward test method for recognition of idle hard blames which create in first info initially… 

References

SHOWING 1-10 OF 11 REFERENCES

An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS

This paper describes an integrated network-on-chip architecture containing 80 tiles arranged as an 8x10 2-D array of floating-point cores and packet-switched routers, both designed to operate at 4

Low-Power NoC for High-Performance SoC Design

TLDR
Emphasizing the application of NoC to SoC design, this book shows how to build the complicated interconnections on SoC while keeping a low power consumption.

Networks on chips - technology and tools

TLDR
This book is the first to provide a unified overview of NoC technology, and includes in-depth analysis of all the on-chip communication challenges, from physical wiring implementation up to software architecture, and a complete classification of their various Network-on-Chip approaches and solutions.

Interconnect limits on gigascale integration

  • J. Meindl
  • Physics
    IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)
  • 1999
Summary form only given. From the inception of microelectronics in 1959 until the early 1990s, transistors dominated both IC performance and cost, while interconnects were of secondary importance. In

Networks on Chips for High-End Consumer-Electronics TV System Architectures

TLDR
This work demonstrates the ideas by extending a commercially-available SOC for picture improvement in high-end TVs with the /Ethereal NOC, the first application of a NOC to a commercial SOC.

The Raw Microprocessor: A Computational Fabric for Software Circuits and General-Purpose Programs

TLDR
The Raw microprocessor research prototype uses a scalable instruction set architecture to attack the emerging wire-delay problem by providing a parallel, software interface to the gate, wire and pin resources of the chip.

Performability/Energy Tradeoff in Error-Control Schemes for On-Chip Networks

TLDR
It is argued in this paper that the use of error-control schemes in on-chip networks results in degradable systems, hence, performance and reliability must be measured jointly using a unified measure, i.e., performability.

Interconnect Opportunities for Gigascale Integration

TLDR
During the past decade, interconnects have replaced transistors as the dominant determiner of chip performance, but new and radically different interconnect technologies will become increasingly important to future gigascale microsystems.

Interconnect limits on gigascale integration Interconnect opportunities for gigascale integration An 80 - tile sub - 100W TeraFLOPS processor in 65 - nm CMOS

  • Networks on Chips : Technology and Tools
  • 2006